Timing over Packet (ToP) Processor for Precision Timing Applications

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Timing over Packet (ToP) processor provides a high-quality, cost-effective solution wherever high-precision timing references are required.
A combination of power-efficient processing, accurate timing capture, generous on-board memory and flexible interface configuration gives the designer confidence that the timing solution designed today will adapt to the requirements of tomorrow. With rate limiting on up to four receive and four transmit queues, priority processing for timing packets is ensured. Each Gigabit Ethernet port has a configurable parser that can be used to filter incoming packets according to a variety of user-defined rules. This gives the user confidence to accommodate new packet formats with just a software update. The integrated digital timing engine supports both IEEE 802.1as and IEEE 1588 synchronization protocols, including hardware timestamping logic and digital PLL for clock recovery.


  • MIPS32® 74K® v2 Core running at up to 600 MHz ensures processing headroom for all timing applications with the ability to process thousands of sync packets per second, while running sophisticated delay variation algorithms
  • Generous allocation of 512 KB of on-chip memory allows standalone operation without use of external DDR
  • Integrated DDR2 Memory Controller with up to 512 MB of memory with two chip selects
  • Provides flexibility in precise clock source and generation by using an on-chip clock reference and direct DPLL output to reduce cost with support for off-chip source and output APLL
  • Digital Timing Engine features Integrated DPPL with sigma-delta modulator and fractional divider, the selection of up to three clock inputs and nanosecond resolution for time-of-day clock
  • Intelligent packet processing can separate sync packets from regular control packet flow for improved algorithm performance
  • Gigabit Ethernet with MAC Layer Timestamp features ContentAware™ processing based on TCAM technology and support for NTP and IEEE 1588 packet classification with priority queuing
  • I/O configuration allows user flexibility in integrating the timing engine with different timestamp capture points


  • Home and Small Business Servers (Processors)
  • Carrier and Service Provider Servers (Processors) 
  • Data Center Servers (Processors)

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