Single 100GbE/Dual 40GbE PHY drives 40G/50G Serial PAM4

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The BCM82251 is a low-power, low-latency PHY integrating retimer and equalizer functions that support 100GbE and 40GbE applications.
In 100GbE mode, the BCM82251 converts 4 × 25GE traffic into 2 × 50GE PAM4 and is capable of driving Direct Attached Cable and SR/LR optics. In 40GbE mode, the BCM82251 converts 2 × 20GE traffic into 1 × 40GbE PAM4, and is capable of driving Direct Attached Cable and SR/LR optics. BCM82251 supports single and dual 40GbE operation. On-chip clock synthesis is performed by a low cost 156.25 MHz reference clock (for all IEEE standard 100GbE/40GbE rates) via high frequency, low-jitter phase-locked loops (PLLs).
The BCM82251 is available in 8mm × 8 mm, 0.65 mm pitch, 144-pin BGA, RoHS-compliant package.


  • Single chip 2x 50G PHY drives 100G over Optics or Copper Cable
  •  Supports both 40GE and 100GE modes
  •  Supports various cable reach/media
  •  Integrated AC Coupling Capacitors
  •  Line and System side Loopbacks
  •  Package 8mm x 8mm BGA, 0.65mm pitch


  • Blade Servers
  • Enterprise LAN Switching
  • Line Cards
  • Routers
  • Servers
  • Switches
  • Top-of-Rack Switches

Lifecycle Status


Specification Value
Lifecycle Active
Distrib. Inventory No
SerDes / GPHY
I/O Bandwidth (Gbps)
Bandwidth UOM
Package 28nm, FPB4NGS, 27mmx27mm
PHY Type 100GE
I/O Controller
Bus Interface
Transfer Rates
External Memory Interfaces 8-bit and 16-bit Flash, w/ 6 Chip Selects SRAM, NVSRAM
ASIC 57301
Link-Speeds 10Gb
Ports 1
TruFlow™ Yes
TruManage™ Yes
Smart Congestion Control No
RoCEv2 No
Multi-Host No
Smart NICs No


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