45G (2 x 23G DQPSK) to SFI-5.1 DeMux

Currently Viewing:

2 x 23G to SFI-5.1 demux for use in 300-pin 40G modules for Differential Quadrature Phase Shift Keying (DQPSK) applications.
The BCM84141 has an OIF SFI-5.1 compliant 16-bit wide transmit system data interface with a deskew channel operating from 2.688 Gb/s to 2.85 Gb/s. The BCM84141 has two clock and data recovery (CDR) circuits that recover the clock and data from the received signals on the two (I and Q) channels, and then demultiplexes and transmits the data on the SFI-5.1 interface. There is an additional deskew lane for the SFI-5.1 interface. The CDRs and demultiplexer are fully integrated. The two-bit data is recovered by two integrated CDRs, respectively. The recovered two-bit data is interleaved to the SFI-5.1 interface along with a deskew channel copying data sequentially from each data channel. The SFI-5.1 timing clock is generated from the recovered clock. The extracted data can optionally be fed to a PRBS detector.


  • Data rate support from 21.5 Gb/s to 22.8 Gb/s
  • Differential I and Q channels
  • Equalizer for PMD and ISI compensation
  • Status indicator for CDR lockdetect
  • RX decision threshold adjust
  • Core power supply: 1.0V

Lifecycle Status


Specification Value
Lifecycle Active
Distrib. Inventory No
Product Brief27 i