Dual 10-Gigabit Ethernet XFI to XAUI™ Transceiver

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Fully integrated dual-serialization/deserialization (10.3125 Gb/s) interface device performing the extension functions for a 10-gigabit serial Ethernet reconciliation sublayer (RS) interface.
The XGXS, PCS and PMA functions include 8B/10B coding, 64B/66B coding, SerDes, clock multiplication unit (CMU), and clock and data recovery (CDR). On-chip clock synthesis is performed by the high-frequency, low-jitter phase-locked loops for the PMD and XAUI™ output retimers. Individual PMD and XAUI clock recovery is performed on the device by synchronizing directly to their respective incoming data streams. Elastic buffers are provided to allow the XAUI and PMD interfaces to operate in asynchronous configuration. Only an external 156.25 MHz oscillator is required for the reference clock input.


  • Dual XFI-to-XAUI 10 GbE transceiver
  • Fully integrated CMU, CDR, SerDes, limiting amplifier and EyeOpener™
  • Meets or exceeds IEEE 802.3ae
  • Supports XFP/XFI and SFP+ interfaces

Lifecycle Status


Specification Value
Lifecycle Active
Distrib. Inventory No
Samples Available No