Quadrature Decoder IC

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The HCTL-2022 is CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-2022 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2022 consists of 4x/2x/1x-quadrature decoder, a binary up/down state counter, and an 8-bit bus interface. The HCTL-2022 has the dual-axis capability and index channel counter. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2022 contains 32-bit counter. It also contains quadrature decoder output signals and cascade signals for use with many standard computer ICs. The HCTL-2022 provides LSTLL compatible tri-state output buffers. Operation is specified for a temperature range from -40 to 100°C at clock frequencies up to 33MHz.


  • Interfaces Encoder to Microprocessor
  • 33 MHz Clock Operation
  • Programmable Count ModesQuadrature (1x, 2x or 4x)
  • Dual Axis Support
  • Index Channel Support
  • High Noise Immunity:Schmitt Trigger Inputs Digital Noise Filter
  • 32-Bit Binary Up/Down Counter
  • Latched Outputs
  • 8-Bit Tristate Interface
  • 8, 16, 24, or 32-Bit Operating Modes
  • Quadrature Decoder Output Signals, Up/Down and Count
  • Cascade Output Signals, Up/Down and Count
  • Substantially Reduced System Software
  • 5V Operation (VDD VSS)
  • TTL/CMOS Compatible I/O
  • Operating Temperature:-40°C to 100°C
  • 32-Pin PDIP, 32-Pin SOIC


  • Interface Quadrature Incremental Encoders to Microprocessors
  • Interface Digital Potentiometers to Digital Data Input Buses

Lifecycle Status


Substance Compliance

  • RoHS6
    Fully Compliant
Specification Value
Lifecycle Active
Distrib. Inventory Yes
Counter Size 32-Bit
Frequency 33MHz
RoHS6 Compliant Y
Package PDIP
Product Type Decoder
Product Change Notice (PCN)5 i