PEX 8609

8 Lane, 8 Port PCI Express Switch, 15 x 15mm PBGA

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The ExpressLane™ PEX 8609 offers 8 PCI Express Gen 2 (5.0 GT/s) lanes, capable of configuring up to 8 flexible ports and fully conforms to the PCI Express Base Specification, rev 2.0. PEX 8609 architecture supports a high-performance DMA engine with four DMA channels and internal buffer space for internal descriptor support. Up to 256 descriptors are supported internally or alternatively descriptors can also exist in host memory. Each descriptor provides support for large transfer sizes (up to 128MB) giving the user the capability to perform very large data transfers in any direction (memory to device, device to device, memory to memory). PEX 8609 also supports cut-thru with the industry's lowest latency of 140ns (x4 to x1) and offers two virtual channels for traffic prioritization in the system. The device also features an on-chip Non-Transparent port for dual-host and failover applications and supports dual-clock domain operation by virtue of support for Spread Spectrum Clock (SSC) isolation, is offered in a 15 x 15mm 324-ball PBGA and is available in both leaded and lead-free packaging. This device supports Access Control Services (ACS).

Lifecycle Status


Specification Value
Lifecycle Active
Dual/ Multi Cast DC
Lanes 8
Latency 140ns
Non-Transparency 1
Packaging Size 15mm X 15mm
PCI-SIG® Base Spec. r2.0
Port Count 8
Power Typ. 1.6
Read Pacing Yes
SSC (Spread Spectrum Clocking ) 1
Temperature -40°C +85°C
Virtual Channels 2
Application Note19 i
Data Book2 i
Design Guide1 i
Design Notes1 i
Errata1 i
HSPICE Model1 i
Quality & Reliability7 i
Rapid Development Kit2 i
Reliability Data Sheet1 i
Selection Guide1 i
Test Report1 i
White Papers3 i

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Software Development Kit (SDK)7 i